{ "ieee_imports": { "prefix": "ieee", "description": "IEEE Standard Packages", "body": [ "library IEEE;", "use IEEE.std_logic_1164.all;", "use IEEE.numeric_std.all;" ] }, "entity_declaration": { "prefix": "ent", "description": "Entity Declaration", "body": [ "entity ${1:$TM_FILENAME_BASE} is", "\tport (", "\t\t$0", "\t);", "end entity ${1:$TM_FILENAME_BASE};" ] }, "architecture_declaration": { "prefix": "arch", "description": "Architecture Declaration", "body": [ "architecture ${1:rtl} of ${2:$TM_FILENAME_BASE} is", "\t", "begin", "\t", "\t$0", "\t", "end architecture ${1:rtl};" ] }, "configuration_declaration": { "prefix": "conf", "description": "Configuration Declaration", "body": [ "configuration ${1:rtl} of ${2:$TM_FILENAME_BASE} is", "\t", "\t$0", "\t", "end configuration ${1:rtl};" ] }, "package_declaration": { "prefix": "pack", "description": "Package Declaration", "body": [ "package ${1:$TM_FILENAME_BASE} is", "\t", "\t$0", "\t", "end package ${1:$TM_FILENAME_BASE};" ] }, "package_body_declaration": { "prefix": "pack", "description": "Package Body Declaration", "body": [ "package body ${1:$TM_FILENAME_BASE} is", "\t", "\t$0", "\t", "end package body ${1:$TM_FILENAME_BASE};" ] }, "case": { "prefix": "case", "description": "Case Statement", "body": [ "case ${1:expression} is", "\twhen ${2:choice} =>", "\t\t$0", "", "\twhen others =>", "\t\t", "", "end case;" ] }, "case_generate": { "prefix": "case", "description": "Case Generate Statement", "body": [ "${1:generate_label}: case ${2:expression} generate", "\twhen ${3:choice} =>", "\t\t$0", "", "\twhen others =>", "\t\tnull;", "", "end generate $1;" ] }, "if": { "prefix": "if", "description": "If Statement", "body": [ "if ${1:condition} then", "\t$0", "end if;" ] }, "if_generate": { "prefix": "if", "description": "If Generate Statement", "body": [ "${1:generate_label}: if ${2:condition} generate", "\t$0", "end generate $1;" ] }, "for": { "prefix": "for", "description": "For Loop", "body": [ "for ${1:loop_var} in ${2:range} loop", "\t$0", "end loop;" ] }, "for_generate": { "prefix": "for", "description": "For Generate", "body": [ "${1:generate_label}: for ${2:iteration} generate", "\t$0", "end generate $1;" ] }, "assert": { "prefix": "assert", "description": "Assertion", "body": [ "assert ${1:neg_condition} report ${2:message} severity ${3|note,warning,error,failure|};" ] }, "enumeration_type": { "prefix": "typeenum", "description": "Enumeration type declaration", "body": [ "type ${1:type_name} is (${0});" ] }, "array_type": { "prefix": "typearray", "description": "Array type declaration", "body": [ "type ${1:type_name} is array (${2:range}) of ${3:element_type};" ] }, "record_type": { "prefix": "typerecord", "description": "Record type declaration", "body": [ "type ${1:type_name} is record", "\t${0}", "end record ${1:type_name};" ] }, "subtype": { "prefix": "subt", "description": "Subtype declaration", "body": [ "subtype ${1:subtype_name} is ${2:base_type} range ${3:0} ${4|to,downto|} ${5:7};" ] }, "testbench_process": { "prefix": "tproc, processt", "description": "Testbench Process (No Sensitivity List)", "body": [ "${1:proc_name}: process", "begin", "\t$0", "end process $1;" ] }, "combinational_process": { "prefix": "cproc, processc", "description": "Combinational Process", "body": [ "${1:proc_name}: process(${2:sensitivity_list})", "begin", "\t$0", "end process $1;" ] }, "asynchronous_reset_clocked_process": { "prefix": "aproc, processa", "description": "Clocked Process (Asynchronous Reset)", "body": [ "${1:proc_name}: process(${3:clk}, ${4:rst})", "begin", "\tif ${4:rst} = ${5:rst_val} then", "\t\t$0", "\telsif ${2|rising_edge,falling_edge|}(${3:clk}) then", "\t\t", "\tend if;", "end process $1;" ] }, "synchronous_reset_clocked_process": { "prefix": "sproc, processs", "description": "Clocked Process (Synchronous Reset)", "body": [ "${1:proc_name}: process(${3:clk})", "begin", "\tif ${2|rising_edge,falling_edge|}(${3:clk}) then", "\t\tif ${4:rst} = ${5:rst_val} then", "\t\t\t$0", "\t\telse", "\t\t\t", "\t\tend if;", "\tend if;", "end process $1;" ] }, "std_logic_vector": { "prefix": "std", "description": "std_logic_vector Type", "body": "std_logic_vector(${1:7} ${2|downto,to|} ${3:0})" }, "std_ulogic_vector": { "prefix": "stdu", "description": "std_ulogic_vector Type", "body": "std_ulogic_vector(${1:7} ${2|downto,to|} ${3:0})" }, "signed": { "prefix": "si", "description": "signed Type", "body": "signed(${1:7} ${2|downto,to|} ${3:0})" }, "unsigned": { "prefix": "uns", "description": "unsigned Type", "body": "unsigned(${1:7} ${2|downto,to|} ${3:0})" }, "zeroes": { "prefix": "oth", "description": "Zero Others", "body": "others => '0'" }, "integer_range_limitation": { "prefix": "intr", "description": "Integer (Range Limitation)", "body": "integer range ${1:0} ${2|downto,to|} ${3:255}" } }